(1) Field of the Invention
The present invention relates to methods of fabricating semiconductor devices, and more specifically to a method for passivating defects on a semiconductor substrate wherein the defects are a result of plasma etching procedures.
(2) Description of Prior Art
Dynamic Random Access Memory (DRAM) devices require specific elements to retain induced charge for significant periods of DRAM operation. The ability of the DRAM elements to retain charge, or data retention time, is strongly influenced by the perfection or defect density of the portion of semiconductor substrate used for DRAM stored charge elements. Unwanted defects in portions of the semiconductor substrate will result in charge leakage, low retention time, and thus poor device yield and performance. Unfortunately several semiconductor device fabrication procedures can create defects in semiconductor substrates thus challenging the ability to fabricate efficient DRAM devices. Plasma dry etching processes such as reactive ion etching (RIE), specifically high density plasma procedures performed to define many critical features in scaled down (smaller geometries) semiconductor devices, can result in damage in the form of defect generation at semiconductor substrate. These defects lead to unsaturated chemical bonds at the semiconductor surface promoting charge leakage from storage elements of a DRAM device. The data retention time loss or charge leakage mechanisms suffered by DRAM devices can be in the form of junction leakage and defect assisted gate induced drain leakage (GIDL).
The present invention will feature passivation of the surface defects caused by high density plasma etching procedures via introduction of a passivating dopant at the semiconductor surface performed after high temperature fabrication procedures have already been executed thus maintaining the passivating dopant at or near the surface of the semiconductor substrate. Numerous attempts at improving data retention time have focused on semiconductor substrate defect reduction, however most of these works involve major and costly process or design modification. Prior art such as Schmitt et al U.S. Pat. No. 4,332,627, as well as Colombo et al US Pat. No. US2004/0127000 A1, teach methods of eliminating process induced defects via use of high temperature anneals after arsenic processing, however these prior art result in arsenic being driven into the semiconductor substrate away from the top surface where plasma etch induced defects are formed. Other prior art such as Cote et al U.S. Pat. No. 6,483,172 B1, Yamaguchi et al U.S. Pat. No. 6,709,906 B2, Fowler U.S. Pat. No. 3,849,204, Solomon et al U.S. Pat. No. 6,803,266 B2, Derycke US Pat. No. US2004/0104406 A1, and Grasser et al U.S. Pat. No. 4,835,006, disclose various processes and procedures for reduction of semiconductor defects, however none of these features of the present invention in which surface defects are reduced via use of specific group V elements introduced at a point in the fabrication process wherein all high temperature procedures have already been performed.